The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2000
Filed:
Feb. 04, 1999
Gary R Lawman, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
The invention provides a structure and method for configuring an FPGA from a PROM using a boundary scan chain. A PROM is provided that comprises JTAG circuitry. Configuration data is stored in the PROM memory as in known PROMs. When the data is retrieved from the PROM memory it is provided on a standard JTAG Test Access Port (TAP). The JTAG-compatible PROM is included as part of a JTAG scan chain, preferably directly preceding the FPGA to be configured by the PROM. The PROM can be controlled either externally or via JTAG commands received down the scan chain. Therefore, a reconfiguration of the FPGA can be initiated via standard JTAG commands. In one embodiment, the PROM itself is programmed with the FPGA configuration data using the JTAG TAP port.