The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2000
Filed:
Oct. 15, 1997
Applicant:
Inventors:
Lucian R Albu, New York, NY (US);
Barry K Britton, Orefield, PA (US);
Wai-Bor Leung, Wescosville, PA (US);
Richard G Stuby, Jr, New Tripoli, PA (US);
James A Thompson, Schnecksville, PA (US);
Zeljko Zilic, Allentown, PA (US);
Assignee:
Lucent Technologies Inc., Murray Hill, NJ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
326 39 ; 326 37 ; 326 38 ;
Abstract
A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.