The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2000
Filed:
Apr. 24, 1998
Sony Corporation, Tokyo, JP;
Abstract
It is intended to provide an electronic material which permits not only PZT but also SBT requiring high-temperature annealing to be used as the material of a dielectric film of a dielectric capacitor in vertical alignment with a transistor so as to connect the lower electrode of the dielectric capacitor to a diffusion layer of the transistor with a Si or W plug; its manufacturing method; and a ferroelectric capacitor and nonvolatile memory. There is also provided a semiconductor device permitting greater freedom in selecting the process temperature and time in a later step subsequent to formation of the plug. Used as the material of the lower electrode of the dielectric capacitor is a material expressed by the composition formula Pd.sub.a (Rh.sub.100-x-y-z Pt.sub.x Ir.sub.y Ru.sub.z).sub.b O.sub.c where a, b, c, x, y and z are composition ratios in atomic %) in which the composition ratios satisfy 70.gtoreq.a.gtoreq.20, 40.gtoreq.b.gtoreq.10, 60.gtoreq.c.gtoreq.15, a+b+c=100, 100>x.gtoreq.0, 100>y.gtoreq.0, 100>z.gtoreq.0 and 100>x+y+z.gtoreq.0. This material is also used as the material of a diffusion preventing layer interposed between the diffusion layer of the semiconductor device and the overlying plug.