The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2000
Filed:
Mar. 31, 1998
Seiji Sogo, Kyoto, JP;
Matsushita Electronics Corporation, Osaka, JP;
Abstract
An N.sup.- - region is formed by diffusion on a P- semiconductor substrate, and a P- region is formed in a surface portion of the N.sup.- - region. A P.sup.+ - region is formed in an outer peripheral portion of the N.sup.- - region, to suppress expansion of a depletion layer of the P- semiconductor substrate when a high voltage is applied. A gate oxide film is formed on the semiconductor substrate, and a gate electrode of polycrystalline silicon is formed on the gate oxide film, particularly on a channel region which is formed by the semiconductor substrate and the P.sup.+ - region, which is as a whole the same as a structure of a lateral N-channel MOSFET. Circuit elements are formed within the N.sup.- - region, and a high voltage is applied. Circuit portions are isolated as the gate electrode and a source region are grounded. This reduces the number of steps for manufacturing a high-insulation IC, increases a breakdown voltage, and integrates the circuit denser.