The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2000

Filed:

May. 27, 1997
Applicant:
Inventors:

Hsingya Arthur Wang, Saratoga, CA (US);

Jein-Chen Young, Milpitas, CA (US);

Ming-Sang Kwan, San Leandro, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438258 ; 438264 ;
Abstract

A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the substrate. The memory cells are fabricated in the second well and have source and drain regions opposite the conductivity type substrate. Each of the first and second wells also includes a region of corresponding conductivity type to enable separate electrical connections to be made to each of the wells.


Find Patent Forward Citations

Wang, Hsingya. (2000). Triple well flash memory fabrication process (U.S. Patent No. 6043123). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6043123

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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