Programmable delay timing calibrator for high speed data interface

Abstract

A graphics processing system incorporates a calibrator module into the system. As a memory module continuously transmits a model data signal, the calibrator module automatically increments the number of stages of delay, which are integrated into a delayed clock signal. Each delayed clock signal triggers the sampling of the model data signal by a plurality of latches. The calibrator module compares each of these sampled data signals with the original model data signals. If the delayed clock signal is properly aligned with the model data signal to cause the two signals to match, the calibrator module stores a result signal in a '1' logic state. If the delayed clock signal is misaligned with the model data signal, the calibrator module will store the result signal in a '0' logic state. When all of the possible stages of delay have been activated by the calibrator module and the corresponding sampled data signals analyzed, a processor module determines the optimum number of stages of delay needed for proper alignment of the delayed clock signal with the transmitted model data signal