Network traffic by instruction packet size reduction

Abstract

Network congestion is mitigated through instruction size reduction. Server instruction to client is stored in most-recently-used cache, such that subsequent retransmission attempt of such instruction is detected, avoided, and instead executed locally from cache. Storage performance is tuned optimally to achieve partial avoidance effect according to graphical or text types, and dynamically adaptable as instruction characteristic changes. MRU FIFO cache provides processors with local checking of new instructions in process for network transmission against most recently executed instructions, thereby avoiding repeat transmissions of instructions already accessible locally. More than one instruction set or packet may also be evaluated, stored and monitored similarly, but instruction subsets may be executed selectively. Each processor maintains same cache information synchronously.