The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2000
Filed:
Nov. 14, 1997
Dao-Long Chen, Fort Collins, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising: a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Also, a PLL circuit for recovering a clock signal from incoming data, comprising: a clock generator for generating an odd number, n, of phase-shifted adjacent clock signals; a data sampler for sampling the incoming data; a first pair of outputs from the sampler, for use in a phase detector (along with a reference clock of the adjacent clock signals and the incoming data), capable of producing an adjustment output. Another characterization is a method for recovering data in a PLL comprising the steps of: generating n phase-shifted adjacent clock signals for sampling bits incoming to the PLL; wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Similarly, a third of the adjacent clock signals can be used to clock bits 2, 2+n, 2+2n, . . . , as well as a fourth and fifth of the adjacent clock signals.