The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2000
Filed:
Jun. 17, 1998
Applicant:
Inventors:
Charvaka Duvvury, Plano, TX (US);
E Ajith Amerasekera, Plano, TX (US);
Sridhar Ramaswamy, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H02H / ;
U.S. Cl.
CPC ...
361 56 ;
Abstract
A method for achieving improving ESD protection in integrated circuits. Capacitance associated with a power supply plays an important role in ESD protection and increasing Vcc.sub.-- c capacitance by integrating distributed capacitors as junction capacitors, or MOS capacitors along Vcc and grounded n+ diffusion parallel runs improves protection against ESD and EOS. Additionally, at least a pair of antiparallel diodes interposed between the periphery voltage source and internal core circuitry voltage provides an added noise margin.