The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2000

Filed:

Jul. 28, 1993
Applicant:
Inventor:

Bruno Ferrario, Fino Mornasco, IT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06G / ; H03B / ;
U.S. Cl.
CPC ...
327344 ; 327553 ; 327552 ;
Abstract

An integrated capacitance multiplier circuit utilizes a pair of field effect transistors, biased in a conducting state, as virtual resistances of a classic operational amplifier network for implementing a capacitance multiplier function. The two field effect transistors have different sizes from each other for attaining a given ON-resistance ratio. A biasing circuit provides independently adjustable biasing voltages for the two field effect transistors. At least one of the two biasing voltages produced by the biasing circuit can be made dependent on temperature according to a certain dependency law in order to exploit the capacitance multiplier circuit for temperature compensating an integrated RC circuit employing the virtual capacitance provided by the multiplier circuit.


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