Address generating circuit for block repeat addressing for a pipelined

Abstract

An address generating circuit of simple configuration for repeating a selected block of instructions is provided. An instruction address maintained by program counter 72 is compared to register 76 that holds the address of the end of the selected block of instructions. When the end address is detected, the program counter is loaded with a starting address of the block of instructions, which is stored in register 80. Block repeat count register 86 maintains a repeat count. Zero detection circuit 70 delays decrements of register 86 by a number of clock cycles that is equivalent to a pipeline depth for instruction prefetching of a processor connected to program counter 72. The zero detection circuit 70 outputs a loop-end control signal which controls a selector to selectively provide an incremented address or the start address to the program counter. By delaying decrements of register 86, the state of the repeat count is correctly maintained when the processor pipeline is flushed during an interrupt. The zero detection circuit also deactivates the loop-end control signal for the number of clock cycles equivalent to the depth of the prefetch pipeline during the final repeat loop iteration(s) so that a loop with a block size less than or equal to the depth of the prefetch pipeline can be repeated the correct number of times.