The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2000

Filed:

Aug. 13, 1997
Applicant:
Inventors:

Shinichiro Suzuki, Tokyo, JP;

Yoichiro Takeuchi, Urawa, JP;

Tadashi Ishikawa, Tokyo, JP;

Ikuo Uchihori, Tokyo, JP;

Takayuki Yagi, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
710260 ; 710260 ; 710261 ; 710262 ; 711200 ; 711202 ; 711210 ; 712244 ;
Abstract

In executing indivisible operations to be executed without being interrupted, pseudo-store instructions PST which do not perform data writing are used to perform a check for the presence or absence in a memory of pages necessary for execution of the indivisible operations. In the event of absence of the necessary pages, the necessary pages are pre-stored in the memory. This prevents the generation of page fault interruptions during the execution of an indivisible operation, thereby enabling the indivisible operation to be implemented on a software basis. A disable interrupt instruction is executed prior to the execution of the indivisible operation as required, and data indicating an address of the disable interrupt instruction is preserved in order to return to the disable interrupt instruction. In the case where an interruption, such as a page fault interruption, which cannot be disabled even in a interrupt disabled state is generated during data processing, processing is resumed from the disable interrupt instruction after the termination of processing for the interruption or an asynchronous interruption, with reference to the address.


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