Single ended read scheme with segmented bitline of multi-port register

Abstract

A read system for a multi-ported register file includes a segmented bit line coupled to a global bit line. Each local bit line segment is coupled to a sub-set of the register files in a column to reduce device load and connection load. The local bit line segments are each coupled in series by local sense amps with the local bit line segment coupled to the input of a global sense amplifier. The number of cells coupled to the last bit line segment is more than the number of cells coupled to a bit line segment farthest from the global sense amplifier to balance device and interconnect load and provide for uniform read timing. Both the local bit line segments and global bit line are precharged prior to sensing a bit so that the local sense amplifiers do not require output pull-up transistors. This scheme will not work if the local sense amp includes a pull-up PMOS transistor at its output.