Semiconductor memory capable of detecting memory cells with small

Abstract

A semiconductor memory comprises: at least two word lines; at least two bit lines which are arranged in a manner crossing the word lines; a reference potential generating circuit for generating a predetermined reference potential; reference potential transfering circuits for transfering the reference potential to the bit lines; at least two memory cells arranged at intersections of the word lines and the bit lines; a sense amplifier for amplifying potential difference between the bit lines; a test mode determination circuit for detecting signal information for starting a predetermined test; and a sense time control circuit taking an output signal from the test mode determination circuit as its input so as to control an operation delay time of the sense amplifier and the word lines. According to the test mode under the present structure, conditions for read-out are more strict, and thus memory cells with small margins, with a small storage capacity, or with a little storage voltage, and a sense amplifier with a low amplification sensibility with respect to the difference potential between the bit lines can be easily detected.