The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2000

Filed:

Sep. 14, 1998
Applicant:
Inventors:

Joo-young Lee, Kyungki-do, KR;

Ki-nam Kim, Kyungki-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438253 ;
Abstract

Integrated circuit memory devices are fabricated by forming a first contact hole in a cell array region and a second contact hole in a peripheral circuit region. Conductive material is simultaneously placed in the first and second contact holes such that the conductive material in the first contact hole electrically contacts a memory cell transistor in the cell array region and the conductive material in the second contact hole electrically contacts the peripheral circuit transistor in the peripheral circuit region. A capping layer is included, and the peripheral circuit region wiring layer and the capacitor storage electrode is formed directly on the capping layer. Improved performance and reduced step height may thereby be obtained.


Find Patent Forward Citations

Lee, Joo-young. (2000). Fabricating methods including capacitors on capping layer (U.S. Patent No. 6037215). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6037215

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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