The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 2000
Filed:
Mar. 12, 1999
Scott T Dupuie, Buda, TX (US);
Richard A Johnson, Buda, TX (US);
Ben W Jones, Austin, TX (US);
Mauricio A Zavaleta, Austin, TX (US);
Mark E Burchfield, Austin, TX (US);
Burton A Devolk, Cedar Park, TX (US);
Franklin W Mayo, Houston, TX (US);
Michael L Abrams, Houston, TX (US);
Roger Maher, Terenure, IE;
I/O of Austin, Inc., Austin, TX (US);
Abstract
A method and apparatus for measuring and compensating for stray capacitance of a micro-machined sensor of an accelerometer system is disclosed. Stray capacitance differences between a top plate and a sensing element and between a bottom plate and the sensing element degrade accelerometer performance if not compensated for. Measurement of stray capacitance difference is achieved by operating the accelerometer in two calibration phases and measuring the steady-state output voltage in each of the two phases. In calibration phase 1, no force is applied to the sensor during clock intervals 1-4. In calibration phase 2, a dummy force up is applied and then a dummy force down is applied during those intervals 1-4. The difference in the output voltage of the two calibration phases is representative of the difference in stray capacitance of the sensor. Capacitance is added to the top or bottom plates in an amount proportional to the measured stray capacitance. The procedure is repeated until the voltage difference of the two calibration phases is zeroed, which is indicative that the inherent stray capacitance has been zeroed.