The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2000
Filed:
Dec. 16, 1997
Larry C James, West Columbia, SC (US);
NCR Corporation, Dayton, OH (US);
Abstract
A method, implemented in hardware, to successively obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within a specified address range within system memory. Whenever the processing node generates a transaction requiring access to a memory address within the specified address range, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. The specified address range is defined by an address value contained within a range counter. The range counter is initially loaded with a starting address value, defining a first group of page addresses to monitor. This address value is periodically incremented up to a preset maximum address value to define successive groups of page addresses to be monitored. Thus, a record of memory access patterns to successive portions of system memory is created which can be used to optimize memory and process assignments in the computer system.