Computer architecture using packet switches for internal data transfer

Abstract

A computer architecture includes a plurality of computer components, a packet switch bank and a plurality of packet interfaces each connecting a corresponding one of the computer components to the packet switch bank, wherein the computer components communicate via the packet switch bank through the plurality of packet interfaces. The packet switch bank can include a plurality of packet switches and a packet switch controller connected to each of the plurality of packet switches. The packet switch controller can thus control each packet switch to be coupled to specific computer components. The packet switch bank can further include a plurality of queues between the packet switches and the computer components. Also provided is a method of communicating from a first component of a computer system to a second component of the computer system, including the steps of transmitting a packet from the first component to a packet switch bank, selecting a packet switch from a plurality of packet switches in the packet switch bank to handle the packet, configuring the selected packet switch to be coupled at an input side to the first component, configuring the selected packet switch to be coupled at an output side to the second component, and transferring the packet through the selected packet switch to the second component.