The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2000

Filed:

May. 14, 1998
Applicant:
Inventors:

Kunihiko Suzuki, Tokyo-to, JP;

Kazuhiro Shibano, Yokohama, JP;

Assignees:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Asia Electronics Inc., Tokyo-To, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365201 ; 36518907 ; 365191 ; 365210 ;
Abstract

A semiconductor memory testing apparatus of the present invention includes a signal generating unit for generating an input signal, an address signal and an expected value signal, a judging unit for judging a quality by comparing the output signal outputted by a semiconductor memory device under test with the expected value signal and generating a judgement signal, and a defect analyzing memory unit having a defect analyzing memory for storing the judgement signal. An address space of the address signal generated by the signal generating unit is set according to classification of the memory cells of the semiconductor memory device under test, and the signal generating unit includes an address space switching unit for switching over the address space as the necessity may arise. The defect analyzing memory unit sets a predetermined address in accordance with the address space to which the address signal belongs.


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