Nonvolatile dynamic random access memory with ferroelectric capacitors

Abstract

A nonvolatile DRAM is disclosed, which comprises a plurality of word lines, at least one plate line, at least a pair of bit lines arranged to intersect the word lines, and a plurality of memory cells each having two access transistors and two ferroelectric capacitors, which are connected between the bit lines. One electrode of each of the capacitors is connected through a corresponding access transistor to a corresponding one of the bit lines. The access transistors are commonly connected with corresponding ones of the word lines. The other electrodes of the capacitors are commonly connected with the plate line. Also provided is a voltage supply circuit for supplying the plate line with one of first and second voltages. In addition, a precharge circuit is included to sequentially precharge the pair of bit lines with the first, the second, and a third voltage in response to first, second, and third precharge signals before a data write/read operation, and then with the third, second, and third voltages after the data write/read operation.