The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 29, 2000

Filed:

Dec. 19, 1996
Applicant:
Inventors:

Kuochun Lee, Fremont, CA (US);

Tsung-Yen Chen, Milpitas, CA (US);

Fong Jim Wang, Belmont, CA (US);

Assignee:

Cirrus Logic, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39550011 ; 39550014 ;
Abstract

A method and system to efficiently incorporate engineering change order (ECO) modifications into an integrated circuit layout having configurable gate array cells is provided. In generating the original integrated circuit layout, extra gate array cells are inserted into the layout. These gate array cells can be reconfigured to modify their functionality according to changes specified by the ECO. A new netlist with a description of the required modifications is generated and provided to a place-and-route CAD tool to create a new layout of the integrated circuit.


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