The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 29, 2000

Filed:

Jul. 30, 1997
Applicant:
Inventors:

Ravi Kumar Kolagotla, Breinigsville, PA (US);

Santosh K Misra, Allentown, PA (US);

Jiancheng Mo, Allentown, PA (US);

Hosahalli R Srinivas, Allentown, PA (US);

Assignee:

Lucent Technolgies Inc., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06M / ;
U.S. Cl.
CPC ...
377 29 ; 377 51 ; 377116 ;
Abstract

An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first input, a test carry signal as a second input, and a control input, the switchable device being capable of providing one of its inputs as an output, the control input capable of controlling selection of the output which is a carry signal. The subcounter also includes an n/k-bit counter, the n/k-bit counter receiving the carry signal and providing n/k output bits, and logic for combining the n/k-bits output from the n/k bit counter with the carry-out signal from an adjacent subcounter to provide an output that is a carry-out signal from the subcounter. The logic introducing a single gate delay between the carry-out signal from the adjacent subcounter and the carry-out signal from the subcounter.


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