The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 29, 2000
Filed:
Mar. 16, 1998
Hee-Choul Park, Kyungi-do, KR;
Eun-Cheol Kim, Kyungi-do, KR;
Samsung Electronics, Co., Ltd., Suwon, KR;
Abstract
A burst SRAM device is provided having a burst column selection circuit which is activated in accordance with a burst address, in addition to a column selection circuit for selecting columns of a memory cell array capable of storing a binary data. An internal column address portion of an external column address is applied to the column selection circuit as a first burst address signal. The column selection circuit selects at the same time at least two columns in response to the first burst address signal. During a burst read mode, at least two columns are simultaneously selected in response to the first burst address signal, and data stored in the selected cells are simultaneously sensed and amplified by at least two sense amplifiers corresponding to the selected memory cells. The data amplified thus are stored in a data output register. The burst addresses are applied to the burst column selection circuit. The burst column selection circuit allows the data stored in the data output register to be sequentially delivered to input/output data line pair in response to the burst addresses. As a result, an interval between a generation time of the first burst address and the time, which takes for a sensing operation of the last 1-bit data to be completed by the last burst address, can be considerably shortened as compared with the conventional device. During a burst write mode, at least two columns are simultaneously selected by the first burst address, and 1-bit data from the input/output data line pair corresponding to locations of the first burst address of the data input register are stored. The burst column selection circuit allows the data delivered sequentially from the data line pair to be sequentially stored in regions of the other burst addresses of the data input register in response to the other burst addresses. At least 2-bit data stored in the data input register are sequentially or simultaneously written in the selected memory cells of the selected columns.