The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 29, 2000
Filed:
May. 07, 1998
Douglas A Mercer, Bradford, MA (US);
Analog Devices, Inc., Norwood, MA (US);
Abstract
A differential current switch including a differential switch pair of transistors having first and second complementary control inputs which receive first and second complementary signals so as to be controlled by a control signal with equal delay from a clock signal. A first set of switching transistors is coupled to provide the first complementary signal which controls the first complementary control input of the differential switch pair. A second set of switching transistors is coupled to provide the second complementary signal which controls the second complementary control input of the differential switch pair. First delay transistor pairs are coupled to the complementary outputs of the cross coupled inverter and have the characteristic that the fall times of its outputs are greater than the rise time of its outputs. Second delay transistor pairs are coupled to the first delay transistor pairs and have the characteristic that the rise times of its outputs are greater than the fall times of its outputs. The second delay transistor pairs are coupled to the first and second sets of switching transistors such that a first output of the second delay transistor pairs provides a first input signal to the first set of switching transistor pairs and a second input signal of the second set of switching transistor pairs, and a second output of the second delay transistor pairs provides the second input signal to the first set of switching transistor pairs and the first input signal of the second set of switching transistor pairs.