High speed sensing of dual port static ram cell

Abstract

The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred embodiment of the invention where the supply voltage is 3.0 volts, the two NFET transistors result in a voltage drop of 2.0 volts so as to produce a reference precharge signal or a bit line precharge signal having a voltage of 1.0 volts. When a precharge enable signal is on, the PFET transistor is connected to ground and is barely on such that the path from the reference precharge signal or the bit line precharge signal to ground is a low impedance path. Moreover, the path from the reference precharge signal or the bit line precharge signal to the supply voltage is also of low impedance. Accordingly, the voltages present at the reference precharge signal or the bit line precharge signal are substantially noise free. The invention also utilizes a unique sense amp that quickly detects changes in the voltage level of a bit line in relation to the voltage level of the reference precharge signal. The sense amp uses an NFET transistor driven by the reference precharge signal which causes the NFET transistor to barely conduct current. This results in dramatically increasing the reaction time of the invention's sense amp. Moreover, because the invention utilizes low bit line and reference precharge voltages, the invention's sense amp is very sensitive to small changes in the bit line voltage relative to the reference precharge voltage.