Multi-bank integrated circuit memory devices having cross-coupled

Abstract

Multi-bank integrated circuit memory devices include first and second memory cell arrays having first and second pairs of differential bit lines electrically coupled thereto, respectively. A dual sense amplifier is also provided and this sense amplifier is electrically coupled together by a first pair of differential input/output lines. First and second isolation circuits are also provided. The first isolation circuit is electrically coupled to the first pair of differential bit lines and is responsive to a first control signal (C1). The second isolation circuit is electrically coupled to the second pair of differential bit lines and is responsive to a second control signal (C2). First and second equalization circuits are provided. The first equalization circuit is responsive to the second control signal and performs the function of equalizing a potential of the first pair of differential bit lines. The second equalization circuit is responsive to the first control signal and performs the function of equalizing a potential of the second pair of differential bit lines. These first and second control signals are generated by a control signal generator, in response to a row address.