Data processing apparatus, system and method for if, then, else

Abstract

A data processing apparatus employs write priority to permit a data processing apparatus to execute an if, then, else operation in a single instruction cycle. The data processing apparatus includes pipelined data unit (110) and address unit (120) operations. The address unit (120) data move operation has a higher write priority than the storing of the data unit (110) operation. The data unit (110) includes an arithmetic logic unit (230) that performs an unconditional operation with the result to be stored in a destination register (200). The address unit (120) sets the address for a data move operation to the same destination register (200). The data move operation is conditional upon the if condition set by the instruction and based upon a set of status bits in a status register (210). The status register (210) includes a plurality of status bits set corresponding to a prior arithmetic logic unit (230) result. The status bits preferably include a negative status bit, a carry status bit, an overflow status bit and a zero status bit. This address unit (120) data move operation, having a higher write priority than the data unit (110) operation, controls the data written into the destination register (200). If the status bits do not match the condition specified in the instruction, then the conditional data move does not take place and the results of the data unit operation are stored in the destination register (200).