The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2000
Filed:
Dec. 09, 1998
William F Baxter, Holliston, MA (US);
Robert G Gelinas, Westboro, MA (US);
James M Guyer, Northboro, MA (US);
Dan R Huck, Shrewsbury, MA (US);
Michael F Hunt, Ashland, MA (US);
David L Keating, Holliston, MA (US);
Jeff S Kimmell, Chapel Hill, NC (US);
Phil J Roux, Holliston, MA (US);
Liz M Truebenbach, Sudbury, MA (US);
Rob P Valentine, Auburn, MA (US);
Pat J Weiler, Northboro, MA (US);
Joseph Cox, Middleboro, MA (US);
Barry E Gillott, Fairport, NY (US);
Andrea Heyda, Acton, MA (US);
Rob J Pike, Northboro, MA (US);
Tom V Radogna, Westboro, MA (US);
Art A Sherman, Maynard, MA (US);
Michael Sporer, Wellesley, MA (US);
Doug J Tucker, Northboro, MA (US);
Simon N Yeung, Waltham, MA (US);
Data General Corporation, Westboro, MA (US);
Abstract
A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.