Integrated circuit memory device with hierarchical work line structure

Abstract

A dynamic random access memory device includes sub-word line drivers to drive sub-word lines up to a boosted voltage level. Each sub-word line driver generates a sub-word drive signal to drive a corresponding sub-word line in response to main-word decode signal and a sub-word decode signal. Each of the sub-word line drivers includes an N-channel MOS pull-up transistor and an N-channel MOS precharge transistor whose threshold voltages are different from each other. The conduction path of the pull-up transistor is coupled between the sub-word decode signal and the corresponding sub-word line. The precharge transistor has a conduction path coupled between the main-word line and the control electrode of the pull-up transistor. The control electrode of the precharge transistor is coupled to the boosted voltage. The boosted voltage is larger than the power supply voltage by twice the threshold voltage of the pull-up transistor. The threshold voltage of the precharge transistor is smaller than that of the pull-up transistor.