The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2000

Filed:

Dec. 08, 1998
Applicant:
Inventors:

Ja Moon Choi, Kyoungki-do, KR;

Jae Whan Kim, Kyoungki-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365145 ; 365149 ;
Abstract

The present invention relates a ferroelectric memory device capable of increasing the life time of the ferroelectric memory devices, by removing a reference ferroelectric capacitors with a smaller chip size. According to the present invention, the ferroelectric memory device uses a power supply Vcc as an reference voltage and doesn't have a reference cell consisting of ferroelectric capacitors. A plate voltage generator according to the present invention provides a plurality of voltage levels to a plate electrode of the ferroelectric capacitor at a read operation in order to use a power supply Vcc as a reference voltage of the sense amplifier, in response to first and second control signals, wherein the plate voltage generating means provides to the plate electrode a first voltage level Vcc+.alpha. more than a power supply Vcc by an additional voltage level .alpha. and a second voltage level of the power supply Vcc, in this order, wherein the first voltage level is provided to the plate electrode before the sense amplifier is enabled, wherein the second voltage level is provided to the plate electrode after the sense amplifier is enabled to restor the cell data in the ferroelectric capacitor, and wherein the additional voltage level is selected in a range that the bit line voltage corresponding to the logic data '0' is less than the reference voltage Vcc at the read operation.


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