The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2000

Filed:

Apr. 02, 1998
Applicant:
Inventors:

Masatoshi Kimura, Tokyo, JP;

Hiroaki Sekikawa, Tokyo, JP;

Kaoru Motonami, Tokyo, JP;

Atsushi Amo, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257296 ; 257303 ; 257306 ; 257382 ; 257384 ; 438239 ; 438244 ; 438253 ; 438655 ; 438694 ;
Abstract

In a semiconductor device having a DRAM memo cell and a peripheral circuit, source/drain regions of transistors composing the memory cell are not silicided to restrict a junction leak and to improve a refresh characteristic; surfaces of source/drain regions and gate electrodes of transistors composing the peripheral circuit are silicided to reduce resistance of contacts and resistance of wirings for enabling a high-speed operation; side walls made of insulating material are formed on sides of the gate electrodes of the transistor composing the peripheral circuit to serve as a mask when impurities are injected for forming the source/drain regions; and insulating material laminated in the memory cell serves as a mask against siliciding.


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