The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2000

Filed:

Nov. 10, 1997
Applicant:
Inventor:

David M Brooks, Oceanside, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B07C / ;
U.S. Cl.
CPC ...
209574 ; 209643 ; 209925 ; 1986891 ;
Abstract

A machine for continuously testing and sorting large quantities of miniature capacitor chips, where the chips having electrically conductive surfaces on opposite ends thereof, including a thin, endless belt arranged to pass over a plurality of rotatable pulleys, at least one of which contains outwardly extending pulley drive pins spaced thereabout that match up with a like plurality of first apertures formed in the belt for driving the belt at a controlled speed over a continuous path; a plurality of second apertures formed in the belt and spaced uniformly therealong, each aperture surrounded by a flattened elastomeric mask and having a slot formed therethrough from one surface of the belt to the other surface of the belt; a feeder to feed the chips, a tester to test the chips; a computer for temporarily registering the measured electrical properties of a particular chip within a particular mask in which the chip resides in the belt; and, a binning wheel, pivotally mounted on a shaft for receiving the tested chips from the masks in a controlled fashion, locating chip receptacles that are specific to certain different ranges of measured electrical properties, and transferring each chip received from the belt to one of the receptacles in which the chip exhibits measured electrical properties that fall within the range thereof.


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