The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2000

Filed:

Dec. 03, 1997
Applicant:
Inventor:

Darrell G Hill, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01B / ;
U.S. Cl.
CPC ...
356399 ;
Abstract

A method and apparatus for accurate automated alignment of semiconductor chips (12,14) or thin-film networks includes forming a plurality of vias (16-19,22-25) in each integrated circuit element in respective locations, and moving the integrated circuit elements to bring the corresponding vias into alignment. In one embodiment, the integrated circuit elements (12,14) are moved by inserting a plurality of spindles (36-39) into respective vias in the integrated circuit elements to align the integrated circuit elements. In another embodiment, the integrated circuit elements (40,42) are moved by providing a source of light (48) on one side of the integrated circuit elements and a light sensor (50) on another side of the integrated circuit elements, and moving the integrated circuit elements to maximize the amount of light traversing the vias (44,46). To enable precision alignment of the integrated circuit elements, the vias may be formed with diameter less than 50 .mu.m.


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