Data processing system having an apparatus for tracking a status of an

Abstract

An FPSCR (Floating Point Status and Control Register) mechanism supports out-of-order floating point unit instruction execution. The FPSCR mechanism provides appropriate reporting of exceptions to a re-order buffer implemented within a data processing system to allow precise interrupts during out-of-order instruction execution. Additionally, the FPSCR mechanism allows for the retention of the appropriate status and control history information in an FPSCR rename buffer to allow the floating points status and control register to be maintained as though instructions were being executed in order. Additionally, the FPSCR mechanism generates the FPSCR's sticky exception status in concordance with reporting appropriate status to the previously mentioned re-order buffer and saving history into the FPSCR rename buffer. Furthermore, the FPSCR mechanism generates non-sticky status bits in addition to an FPU pipe state for retention in the FPSCR rename buffer in addition to an instruction issue mechanism that supports the generation of FPU pipe state bits to support calculation of non-sticky status bits stored within the FPSCR. By implementing each of these functions, the FPSCR mechanism permits the out-of-order execution of eligible floating point unit instructions.