Method and apparatus for maintaining coherency for data transaction of

Abstract

A method and apparatus for maintaining coherency in CPU and bus device data transactions in a computer system. A CPU may write data items to a memory shared with bus devices and may also write data items to a write buffer in a bridge circuit which are to be sent out on a device bus, such as a PCI bus. When the CPU writes a data item to the shared memory after writing a data item to the write buffer, a dirty bit is set for each location in the write buffer that stores a data item. When a bus device requests access to the shared memory, the dirty bits are checked. If the dirty bits are set, the bus device is denied access to the shared memory to maintain write coherency. When bus device access is denied, the bus device is informed to retry its request at a later time, and data items in the write buffer are flushed to devices on the bus. The write buffer is disabled after flushing the data items so that the CPU cannot write additional data items to the write buffer until the bus device has retried and accessed the shared memory.