Clock recovery circuit and method for mpeg-2 system decoder

Abstract

A clock recovery circuit and method for an MPEG-2 system decoder. The clock recovery circuit comprises a digital signal processor including a controller, a PCR/SCR detector, an adder/subtracter unit, a digital filter and a register, a DAC, a low pass filter, a voltage controlled oscillator and a counter. The counter generates a clock value of a desired number of bits. The PCR/SCR detector receives a transport or program stream and detects a PCR or SCR therefrom. The controller checks whether the detected PCR or SCR is an initial value. If the detected PCR or SCR is the initial value, the adder/subtracter unit subtracts the clock value from the counter from the detected PCR or SCR starting from the least significant bit to generate a first value. If the detected PCR or SCR is not the initial value, the adder/subtracter unit subtracts lower-order bit values of the first value corresponding to the desired number from lower-order bit values of the detected PCR or SCR corresponding to the desired number and subtracts the clock value from the counter from the subtracted result to generate a second value. Then, the adder/subtracter unit transfers the second value to the DAC. Also, the adder/subtracter unit adds the clock value from the counter to the first value starting from the least significant bit to generate a system time clock.