Semiconductor memory device having bit lines and signal wiring layers

Abstract

A semiconductor dynamic random access memory device has a switching transistor fabricated on a first area of a silicon substrate, another switching transistor fabricated on a second area of the silicon substrate and forming a part of a peripheral circuit, a first inter-level insulating structure covering the first and second switching transistors, a bit line formed on the first inter-level insulating structure and electrically connected to the drain region of the first switching transistor, a signal wiring layer formed on the first inter-level insulating structure and electrically connected to the drain region of the second switching transistor, a second inter-level insulating layer covering the bit line and the signal wiring layer and a storage capacitor formed on the second inter-level insulating layer and electrically connected to the drain region of the second switching transistor; parasitic capacitance is the major factor for the signal propagating speed along the bit line, and resistance is the major factor for the signal propagating speed along the signal wiring layer; and the bit line is thinner than the signal wiring layer, because the capacitance between the adjacent bit lines occupies the amount of the parasitic capacitance.