The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2000
Filed:
Nov. 14, 1997
Applicant:
Inventors:
Assignee:
Fujitsu Limited, Kawasaki, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257341 ; 257382 ; 257401 ; 257758 ; 257920 ;
Abstract
A semiconductor integrated circuit includes a gate extending in a first direction, a diffusion-layer region corresponding to the gate, and a plurality of backing wiring lines connected to the diffusion-layer region and extending in a first wiring layer in a second direction substantially perpendicular to the first direction. The semiconductor integrated circuit further includes connection wiring lines providing connections between the plurality of backing wiring lines and provided in a second wiring layer.
Sawamura, Takahiro. (2000). Semiconductor integrated circuit having efficient layout of wiring lines (U.S. Patent No. 6020612). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6020612
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile