Method for forming ldd cmos

Abstract

A method for fabricating a CMOS integrated circuit device with less masking steps than a conventional device. The present method includes a step of providing a semiconductor substrate with a well region, a gate dielectric layer, and a polysilicon gate electrode. The gate dielectric layer is overlying the well region, and the polysilicon gate electrode is overlying the gate dielectric layer. The present method also includes forming a first thermal oxide thickness overlying the polysilicon gate electrode layer and a second thermal oxide thickness overlying exposed regions. The first thermal oxide thickness is greater than the second thermal oxide thickness, and both layers are defined during the same step. A mask exposes first LDD regions and first source drain regions. The present method then angle implants a first impurity through the first thermal oxide thickness and the second thermal oxide thickness, and implants a second impurity through the second thermal oxide thickness, thereby forming the completed source/drain region in a single masking step.