Data processing apparatus and method for generating timing signals for a

Abstract

A self-timed data processing circuit and method of operation of such a circuit are disclosed. The circuit comprises a plurality of components, such as memory cells, arranged to generate substantially simultaneously a plurality of first output signals, each representing variable data bits. A timed circuit, which may include a plurality of sense amplifiers, is then arranged to receive the first output signals and to generate second output signals for use in subsequent data processing operations, the information content of the second output signals being dependent on the data bits represented by the first output signals. A subset of the components, such as memory cells storing dirty and valid bits for a cache memory, are arranged to generate first output signals representing data bits that are coded so as to cause at least one of the second output signals generated by the timed circuit to transition from its state prior to the generation of the first output signals. Control circuitry, responsive to the state transition of the at least one second output signal, is then used to generate a timing signal used to control the operation of the timed circuit to provide reduced power consumption. This also enables a reference timing signal to be created to self-time the data processing circuit, without the need to duplicate the critical path of the data processing circuit by using additional reference components.