High performance shared memory for a bridge router supporting cache

Abstract

An internetwork device manages the flow of packets of I/O data among a plurality of network interface devices. The internetwork device includes an I/O bus which is coupled to the plurality of network interface devices and a shared memory, for storing packets of I/O data and control structures needed by the plurality internetwork interface devices. The shared memory is also coupled to a processor bus, which connects to a processor and a processor memory. The processor memory is isolated from the shared memory, and is used for storing routines and internetworking information involved in routing packets of I/O data among the plurality of network interface devices. In this way, accesses between the processor and the processor memory are decoupled from accesses between the plurality of network interface devices. System performance is improved by storing copies of items from the shared memory in a processor cache located near the processor. Consistency rules are enforced between items in the shared memory and copies of the items in the processor cache through communications across the processor bus. Communications across the processor bus to enforce consistency rules are minimized by maintaining a shadow tag store near the shared memory, which keeps track of the items from the shared memory which are copied in the processor cache. Communications to enforce consistency rules only take place if the shadow tag store indicates that the processor cache contains an item of data from the shared memory which has been read from or written to.