Mock wordline scheme for timing control

Abstract

A mock wordline timing scheme is used in a memory device having a plurality of memory cells arranged in array blocks. The array blocks are further arranged in groups, with each array block being located between a pair of corresponding sense amplifier banks. Each array block has at least one mock wordline, and each sense amplifier bank is shared by the array blocks located on either side of the sense amplifier bank, except the sense amplifier banks located on the ends of the group of array blocks. Each sense amplifier bank has a corresponding sense timing control circuit coupled to receive an enable signal and a timing signal. In response to an address, a row decoder is configured to be selected to drive the addressed word line. In conjunction with the row decoder, the enable and timing signals of the sense amplifier bank adjacent to the array block containing the addressed memory cell are asserted. The row decoder causes the timing signal to be propagated through a mock wordline that is not in the same array block as the addressed memory cell. Thus, memory cells in the active array are not disturbed, which could result in incorrect sensing and data corruption. Further, unlike some conventional schemes, the selected mock wordline is in an inactive array block even if the active array block is at an end of the bank of array blocks.