Method and system which permits logic signal routing over on-chip

Abstract

A method is provided for using twisted bit or signal lines and routing restrictions on the logic signal lines to pass logic signals over an on-chip memory. In one embodiment, the memory array includes complementary bitlines which are provided with periodic twists, and the logic signal routing is restricted in that logic signals are either routed perpendicular to the bit lines, or they are routed parallel to the bit lines in such a manner as to ensure equal coupling to both B and B'. The equal coupling is provided by either restricting the length of the logic signal line segment to an integral number of twist wavelengths, or by placing the logic signal line segment so that its midpoint rests on a twist centerline. In another embodiment, the memory array includes bitlines running parallel to a bitline axis, and complementary logic signal lines are routed in pairs. The logic signal routing is restricted in that logic signals are either routed perpendicular to the bitline axis, or they are routed parallel to the bitlines in such a manner as to ensure equal coupling to both B and B'. The equal coupling is provided by either placing a twist at the midpoint of the complementary logic signal line segment, or by placing periodic twists in the complementary logic signal line segment and restricting the length of the segment to an integer number of twist wavelengths.