The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2000
Filed:
Jun. 26, 1997
David Chiang, Saratoga, CA (US);
Neil G Jacobson, Mountain View, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A programming method of a programmable logic device (PLD) to enable system recovery after power failure is provided. Key configuration bits controlling output enable signals of the PLD are programmed at a different time than all other configuration bits in the PLD. If those key bits are unprogrammed, the PLD behaves identically to a fully erased device. Thus, by programming the key configuration bits after all other bits are successfully programmed, any potential damage to the system is virtually eliminated. In this manner, if the main programming sequence is interrupted, the PLD will power up with partial internal activity, but no active output signals. Moreover, even if the interruption occurs during the programming of these few bits, the result is only a partial activation of output signals which is significantly better than the activation of output signals with incorrect functions.