The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2000

Filed:

Oct. 24, 1997
Applicant:
Inventors:

Shiuh-Luen Wang, San Jose, CA (US);

Chiang-Sheng Yao, Palo Alto, CA (US);

Wen-Chin Yeh, Fremont, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438528 ; 438585 ; 438592 ;
Abstract

A method for hardening of gate oxide without forming low dopant concentration regions at the gate oxide-polysilicon interface is described. Polysilicon is deposited onto gate oxide followed by nitrogen implantation and annealing. At this point nitrogen concentration peaks exist at the gate oxide interfaces with the single crystal substrate and the polysilicon gate electrode. This effectively hardens the gate oxide. A third polysilicon gate electrode exists in the bulk of the polysilicon gate electrode. In the described process the region of the polysilicon layer that contains the nitrogen concentration peak is removed. An electronically active dopant may then be implanted. Alternatively, a fresh polysilicon layer may then be deposited followed by implantation of an electronically active dopant. Thus, the method of the invention avoids retardation of electronically active dopant diffusion.


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