The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2000

Filed:

Dec. 17, 1997
Applicant:
Inventors:

Yuesong He, San Jose, CA (US);

John Jianshi Wang, San Jose, CA (US);

Dae Yeong Joh, Los Altos, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438216 ; 438264 ; 438762 ; 438770 ; 438287 ;
Abstract

This invention relates to a method for forming a low barrier height oxide layer on the surface of a crystalline silicon substrate, comprising: (A) forming spaced field oxide regions on the surface of said crystalline silicon substrate, the space between said field oxide regions comprising a tunnel region; (B) vapor depositing a layer of amorphous silicon on the surface of said field oxide regions and on the surface of said substrate in said tunnel region, the thickness of said layer of amorphous silicon being in the range of about 50 .ANG. to about 100 .ANG.; and (C) oxidizing said layer of amorphous silicon. The oxidized amorphous silicon layer in said tunnel region is a tunnel oxide layer and, in one embodiment, the inventive method includes the step of (D) forming a floating gate over said tunnel oxide layer, said tunnel oxide layer having a barrier height of about 1.6 to about 2.0 eV.


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