Priority arbitration system providing low latency and guaranteed access

Abstract

The present invention comprises a priority arbitration system for interfacing a plurality of PCI agents coupled to a peripheral component interconnect (PCI) bus such that high priority PCI agents are satisfied without starving low priority PCI agents. The system of the present includes a PCI bus adapted to transmit data signals. At least one high priority PCI agent is coupled to the PCI bus. At least one low priority PCI agent is coupled to the PCI bus. An arbiter is coupled to the high priority PCI agent and the low priority PCI agent via the PCI bus. The arbiter grants ownership of the PCI bus to the high priority PCI agent prior to granting ownership to the low priority PCI agent. After being granted ownership, the high priority PCI agent becomes an interim low priority PCI agent. The low priority PCI agent is accorded a higher priority by the arbiter than the interim low priority PCI agent. The interim low priority PCI agent reverts to the high priority PCI agent subsequent to a grant to the low priority PCI agent. In this manner, the arbiter, by granting ownership of the PCI bus to the low priority PCI agent before granting ownership of the PCI bus to the interim low priority PCI agent, ensures the low priority PCI agent is not prevented from accessing the PCI bus by the high priority PCI agent.