The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2000
Filed:
Apr. 06, 1998
Salomon Vulih, Neshamic Station, NJ (US);
Donald R Preslar, Somerville, NJ (US);
Thomas A Jochum, Durham, NC (US);
Intersil Corporation, Palm Bay, FL (US);
Abstract
An integrated circuit sample-and-hold (S/H) circuit includes an amplifier offset compensation circuit for compensating for the D.C. offset of a buffer amplifier. The amplifier offset compensation circuit may include an offset determining circuit for determining an offset voltage generated by the buffer amplifier, and an offset correction circuit for generating an offset correction signal and coupling the offset correction signal to the buffer amplifier. The S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and a first field-effect transistor (FET) formed on the substrate. The first FET may have a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the first sampling capacitor during a sampling time and for disconnecting the input signal from the first sampling capacitor during a holding time. The first FET may further include a body creating a parasitic diode-connected to the first sampling capacitor. To address this parasitic diode, the circuit includes the buffer amplifier having an input connected to the first sampling capacitor and an output connected to the body of the first FET during the holding time. The offset of the buffer amplifier is compensated.