The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2000
Filed:
Dec. 18, 1997
Julian Zhiliang Chen, Dallas, TX (US);
Thomas A Vrotsos, Richardson, TX (US);
Wayne T Chen, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An SCR (68) for protecting an integrated circuit (62) against ESD events is provided having a trigger voltage which is automatically adjusted to different trigger voltage levels in response to power being applied to the integrated circuit (62). An enhancement-type P-channel transistor (78) is provided for determining the trigger voltage. When operating power is not being applied to the integrated circuit (62), the P-channel transistor (78) threshold voltage determines the voltage at which the SCR (68) is triggered. When operating power is being applied to the integrated circuit (62), the operating voltage is applied to the gate of the P-channel transistor (78), and then the operating voltage and the threshold voltage for the P-channel transistor (78) determine the trigger voltage of the SCR (68). Then, a PNP and NPN transistor pair (76, 80) that form the SCR (68) are latched to shunt the protected signal path (69) to ground. The SCR (68) remains latched until the voltage applied to the signal path (69) falls beneath a holding voltage of the SCR (68). A plurality of the SCRs (126, 128) may be connected in series, such that the overall holding voltage for the series of SCRs (126, 128) is approximately equal to the sum of the individual holding voltages for the SCRs (126, 128), which overall holding voltage is greater than the trigger voltage. Preferably, the SCR (68) is isolated from the P substrate (92) by a P-N junction which is provided by disposing the SCR (68) within an N-tank (98).