Damascene formation of borderless contact mos transistors

Abstract

This invention is a processing method for forming MOS transistors. The method uses chemical mechanical polishing to self align an MOS transistor gate electrode to the channel region in both the width and length directions. The method enables metal interconnect lines to make borderless connections to MOS gate electrodes directly over channel regions, and allows borderless connections to be made to source and drain regions, thereby improving layout density of small transistors. The method enables interconnect lines to be patterned on a planar surface, which facilitates the etching of very narrow and closely spaced lines. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon. The method also prevents plasma damage of very thin gate dielectrics during processing.